1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to transistors comprising a gate with a spacer structure formed on its sidewalls. Yet more in particular, the present disclosure relates to an integrated circuit wherein at least two transistors are present having spacer structures with different thicknesses. This situation normally occurs when one of the transistors is an N-channel transistor and the other transistor is a P-channel transistor with a silicon/germanium (SiGe) alloy embedded in the source/drain regions and overfilling the trenches in which it is embedded.
2. Description of the Related Art
Transistors are the dominant components in modern electronic devices. Currently, several hundred millions of transistors may be provided in presently available complex integrated circuits such as microprocessors, CPUs, storage chips and the like. It is then crucial that the typical dimensions of the transistors included in an integrated circuit have as small as possible typical dimensions, so as to enable a high integration density.
One of the most widespread technologies is the complementary metal-oxide-semiconductor (CMOS) technology, wherein complementary field effect transistors (FETs), i.e., P-channel FETs (PFETs) and N-channel FETs (NFETs), are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies.
Transistors are usually formed in active regions defined within a semiconductor layer supported by a substrate. Active regions are to be understood as a portion of the semiconductor layer within which and on top of which a transistor or a semiconductor device may be formed. Presently, the semiconductor layer in which most integrated circuits are formed is made out of silicon, which may be provided in crystalline, polycrystalline or amorphous form. Other materials, such as, for example, dopant atoms or ions, may be introduced into the original semiconductor layer.
A MOS transistor, or generally a FET, irrespective of whether an NFET or a PFET is considered, comprises a source and a drain region, highly doped with dopants of the same species. An inversely or weakly doped channel region is then arranged between the drain and the source regions. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, may be controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region depends on, among other things, the mobility of the charge carriers and the distance along the transistor width direction between the source and drain regions, which is also referred to as channel length. For example, by reducing the channel length, the channel resistivity decreases. Thus, an increased switching speed and higher drive current capabilities of a transistor may be achieved by decreasing the transistor channel length.
However, reduction of transistor channel length may not be pushed to extreme limits without incurring other problems. For example, the capacitance between the gate electrode and the channel decreases with decreasing channel length. This effect must then be compensated for by reducing the thickness of the insulating layer between the gate and the channel. Extremely small thicknesses of the insulating layer might, however, result in increased leakage currents caused by hot carrier injection and direct tunneling of charge carriers through the extremely thin gate dielectric material. Since a further reduction in thickness of silicon dioxide-based gate dielectric materials may increasingly become incompatible with thermal power requirements of sophisticated integrated circuits, other alternatives have been developed in order to increase the charge carrier mobility in the channel region, thereby also enhancing overall performance of field effect transistors.
When fabricating transistors with typical gate dimensions below 50 nm, a so-called “high-k/metal gate” (HKMG) technology is well known and frequently employed. According to the HKMG manufacturing process flow, the insulating layer included in the gate electrode is comprised of a high-k material. On the other hand, it is also well established to use an oxide/polysilicon (poly/SiON) method, whereby the gate electrode insulating layer is typically comprised of an oxide, preferably silicon dioxide or silicon oxynitride in the case of silicon-based devices.
Currently, two different approaches exist for implementing HKMG in the semiconductor fabrication process flow. In the first approach, called gate-first, the fabrication process flow is similar to that followed during the traditional poly/SiON method. Formation of the gate electrode, including the high-k dielectric film and the work function metal film, is initially performed, followed by the subsequent stages of transistor fabrication, e.g., definition of source and drain regions, silicidation of portions of the substrate surface, metallization, etc. On the other hand, according to the second scheme, also known as gate-last or replacement gate, fabrication stages such as dopant ion implantation, source and drain region formation and substrate silicidation are performed in the presence of a sacrificial dummy gate. The dummy gate is replaced by the real gate after the high-temperature source/drain formation and all silicide annealing cycles have been carried out.
HKMG enables increasing the thickness of the insulation layer in the gate electrode, thereby significantly reducing leakage currents through the gate, even at transistor channel typical sizes as low as 30 nm or smaller. However, implementation of HKMG brings about new technological challenges. For example, new materials have to be found in order to tune the work function of gate electrode species, so as to adjust the transistor threshold voltage to a desired level. Thus, in the HKMG technology, a thin metal layer is inserted between the high-k dielectric and the gate material placed above the high-k dielectric. The threshold voltage can thus be adjusted by varying the thickness of the metal layer. The gate metal layer may comprise, for example, tantalum (Ta), tungsten (W), titanium nitride (TiN) or tantalum nitride (TaN). A work function metal, such as aluminum (Al) or lanthanum (La), may be present in a predetermined percentage in the metal layer or may form a separate layer between the metal layer and the high-k dielectric.
One promising strategy for improving speed and performance of a FET consists in the generation of a certain type of strain in the FET channel region, since the charge carrier mobility in silicon strongly depends on the strain conditions of the crystalline material. For example, it has been found that, for a standard crystallographic configuration of the silicon-based channel region, a compressive strain component in a P-channel transistor may result in a superior mobility of holes, thereby increasing switching speed and drive current of P-channel transistors.
Therefore, attempts have been made in the past decades to improve transistor performance by introducing a stress-inducing material in or near the channel region of silicon-based transistors. Stress can be brought about by the difference in lattice constant between the stress-inducing material and silicon. For instance, in order to induce a compressive stress in the channel region of a P-channel transistor, a material with a slightly larger lattice constant than silicon, such as a silicon/germanium (SiGe) semiconductor alloy, may be epitaxially grown in the transistor active region next to or on top of the channel region.
Thus, trenches may be formed in portions of the source and drain regions of a FET adjacent to the channel region. An SiGe alloy, or a semiconductor alloy in general, may subsequently be epitaxially grown in the trenches. This semiconductor alloy is also commonly referred to as an “embedded semiconductor alloy” or, in the particular case of an SiGe alloy, “embedded SiGe”. The embedded semiconductor alloy is then included in the source or drain region of the FET.
According to the gate-first HKMG approach, the gate structure is formed by depositing a stack of layers, which is subsequently appropriately patterned so as to obtain a gate structure of the desired size and dimensions. The gate-first HKMG approach requires the gate electrode stack to withstand the high temperatures reached during the annealing steps performed in order to, e.g., activate the dopant species implanted in the source and drain regions or induce the silicidation process.
Thus, in order to protect the sensitive gate materials during the subsequent fabrication stages, the gate stack is encapsulated into a dielectric casing formed on its sidewall. This protective layer, also known as a “spacer” or “spacer structure,” besides protecting the sensitive gate materials, is advantageously used as a mask when implanting dopants of a desired type into the semiconductor layer in which the transistor is formed. In this respect, the spacer structure may be formed in subsequent stages so as to have the appropriate shape and thickness during each implantation step.
In particular, a first spacer portion having a first thickness is formed next to the encapsulating portion. This first portion is usually called “spacer-0”. A first series of implantations may be performed using the spacer-0 as a mask. This first series may include implantations carried out in order to define halo regions in the transistor channel region and extension regions in the source and drain regions. Subsequently, the spacer structure may be broadened by forming a second portion above the spacer-0 previously formed. This second portion is usually referred to as “spacer-1”. A second series of implantations may then be performed in the presence of both spacer-0 and spacer-1, for example in order to define the deep regions of the source and drain regions.
When forming an array of FETs including NFET and PFET structures, according to the HKMG conventional manufacturing flow, but also if the conventional SiON/polysilicon gate structures are used, problems are incurred if embedded SiGe is used in the source/drain area of PFETs. In both of these cases, spacer structures of different thicknesses are formed on the sidewalls of NFETs and PFETs. This is illustrated in an exemplary manner for an HKMG structure in FIGS. 1a-1e, which show subsequent stages during a conventional HKMG manufacturing flow.
FIG. 1a shows a cross-sectional view of a portion of an integrated circuit 100 in a relatively advanced manufacturing stage. Transistors 151-154 have been partially formed partly in and partly on top of a semiconductor layer 110. Transistors 151-154 are, for example, FETs.
The semiconductor layer 110 is typically supported by a substrate, which may be represented by any suitable carrier for an integrated circuit. The semiconductor layer 110 may comprise, for example, silicon, germanium or also a III-V semiconductor. The semiconductor layer 110 is divided into active zones, which are to be understood as areas of the semiconductor layer 110 in which and upon which one or more FETs may be formed. FIG. 1a shows a first active region 112 housing FETs 151 and 152, and a second active region 114 housing FETs 153 and 154. FETs 151 and 152 may conveniently have an opposite polarity with respect to FETs 153 and 154. For example, FETs 151 and 152 may be N-channel FETS, whereas FETs 153 and 154 may be P-channel FETs.
Active regions 112 and 114 are separated by an isolation region 116, typically comprising an insulating material such as, for example, an oxide. For example, the isolation region 116 may comprise silicon dioxide (SiO2) and may have been formed by means of the shallow trench isolation (STI) technique.
Transistors 151-154 each comprise a respective gate structure 151g-154g. The gate structures 151g-154g shown in FIG. 1a have been formed according to the HKMG technology. Thus, the gate structures 151g-154g are each made up of a stack comprising an insulation layer 161 formed on the surface of the semiconductor layer 110, a gate metal layer 163 and a gate material layer 165.
The insulation layer 161, formed on the surface of active regions 112 or 114, comprises a high-k material. The gate metal layer 163 is formed between the insulation layer 161 and the gate material 165 so as to adjust the transistor threshold voltage. The gate material layer 165, formed directly on the upper surface of the gate metal layer 163, typically comprises a semiconductor such as polysilicon.
Each transistor 151-154 comprises a respective spacer structure 171-174 formed on the sidewall of the respective gate structure 151g-154g. The spacer structures 171-174 comprise a dielectric material which is negligibly affected by the standard wet etching process performed for cleaning purposes on the surface of the integrated circuit. Furthermore, the dielectric material constituting spacer structures 171-174 hinders transport of oxygen or other gases through its thickness. Typically, the spacer structures 171-174 are comprised of silicon nitride (Si3N4).
In the fabrication stage shown in FIG. 1a, spacer structures 171-174 comprise an inner portion 171sp0-174sp0, respectively, known as spacer-0. The spacer-0 structures 171sp0-174sp0 typically comprise Si3N4. As further shown in FIG. 1a, the spacer structures 171-174 may conveniently comprise one or more liner layers 167, used as stop-etch layers when forming the spacer structures 171-174. The liner layer 167 typically comprises an oxide. For example, the liner layer 167 may be comprised of silicon dioxide (SiO2).
The spacer structures 171-174 may be formed by depositing a first liner layer 167i, included in liner layers 167, onto the surface of the integrated circuit 100 after forming the gate structures 151g-154g. Thus, the first liner layer 167i is formed adjacent to the gate structures 151g-154g. Subsequently, a dielectric layer, such as an Si3N4 layer, may be deposited onto the first liner layer 167i and appropriately patterned in order to obtain spacer-0 structures 171sp0-174sp0. Patterning is conveniently achieved by an anisotropic etching selective to the liner layer 167i. The spacer-0 structures 171sp0-174sp0 are, thus, formed adjacent to the gate structures 171g-174g, respectively, and separated therefrom by the first liner layer 167i. 
After forming the spacer-0 structures 171sp0-174sp0, a First Series of Implantations may be performed, for example, in order to form halo regions and extension regions (not shown) of transistors 151-154 in the semiconductor layer 110. Subsequently, a second liner layer 167o, also included in liner layer 167, is deposited onto the surface of the integrated circuit 100. Deposition of the second liner layer 167o is then followed by the deposition of a second dielectric layer 173, e.g., an Si3N4 layer, onto the second liner layer 167o. The dielectric layer 173 is generally deposited by using a highly conformal deposition technique, such as, for example, chemical vapor deposition (CVD). The dielectric layer 173 is subsequently patterned in order to form an outer portion of the spacer structures 171-174 called spacer-1, as will be described in the following.
FIG. 1a shows that semiconductor alloy layers 122-124 are embedded in the second active region 114, next to the gate structures 153g and 154g. The semiconductor alloy layers 122-124 typically comprise embedded SiGe (eSiGe) with a variable Ge concentration. The semiconductor alloy layers 122-124 are obtained by forming trenches in predetermined positions of the active region 114 adjacent to the gate structures 153g and 154g. The trenches are then epitaxially filled with a semiconductor alloy. If FETs 153 and 154 are P-channel FETs, the semiconductor alloy layers 122-124 may be conveniently doped with a P-type doping agent, which may include, for example, boron (B). Doping of the semiconductor alloy layers 122-124 is conveniently performed in situ while epitaxially depositing the semiconductor alloy layers 122-124 in the trenches. Furthermore, if FETs 153 and 154 have a P-channel, the semiconductor alloy in layers 122-124 is typically SiGe. As said above, since SiGe has a larger lattice constant than Si, SiGe layers 122-124 exert a compressive strain onto the areas of the active region 114 directly underneath the gate structures 153g and 154g, which are to be included in the channel regions of FETs 153 and 154, respectively. This is beneficial to the mobility of holes in the channel region of a P-channel FET.
FIG. 1a also shows that, in the case in which semiconductor alloy layers 122-124 comprise SiGe, layers 122-124 each comprise a bottom portion 122a-124a, a middle portion 122b-124b and a top portion 122c-124c. The three portions of the SiGe alloy layers 122-124 differ from each other for the concentration of Ge.
More specifically, bottom portions 122a-124a have a lower Ge concentration than middle portions 122b-124b. For example, the concentration of Ge in bottom portions 122a-124a could be of approximately 25%, whereas the concentration of Ge in middle portions 122b-124b could be of approximately 35%. Thus, bottom portions 122a-124a formed adjacent to the surface of active regions 114 have a smaller lattice constant than middle portions 122b-124b formed above bottom portions 122a-124a, respectively. Since the lattice mismatch with silicon is smaller, bottom portions 122a-124a are affected by a lower degree of internal strain than middle portions 122b-124b, which favors a pseudomorphic epitaxial growth of SiGe layers 122-124 onto the semiconductor layer 110, typically including silicon.
Top portions 122c-124c of SiGe alloy layers 122-124 are then formed above middle portions 122b-124b, respectively. Top portions 122c-124c contain a substantially null concentration of Ge and are exclusively comprised of Si. The presence of top portions 122c-124c is necessary in order to favor the silicidation process subsequently performed on the surface of the integrated circuit 100 in order to form electrical connections to the electrodes of the FETs formed therein. Metal silicide formation is indeed known to be much more easily and reliably achieved in Si than in an SiGe alloy.
The structure of the semiconductor alloy layers 122-124 discussed above results in the trenches being significantly overfilled by the semiconductor alloy material. The semiconductor alloy material of layers 122-124, typically SiGe, can in some cases protrude outwards, for instance, by a height of approximately 15 nm from the plane identified by the surface of the semiconductor layer 110. In general, the semiconductor alloy material of layers 122-124 protrudes typically more than 10 nm, often more than 20 nm from the plane identified by the surface of the semiconductor layer 110.
In FIG. 1b a cross-sectional view is shown of the integrated circuit 100 in a subsequent manufacturing stage to that shown in FIG. 1a. After forming the dielectric layer 173 shown in FIG. 1a, this is patterned in order to give rise to outer portions 171sp1-174sp1 of spacer structures 171-174, respectively, shown in FIG. 1b. Outer portions 171sp1-174sp1 are also known as spacer-1 structures. Patterning is usually achieved by means of a dry etching selective to liner layer 167, in such a way that the second liner layer 167o acts as a stop-etch layer. The dry etching process is preferably highly anisotropic. Patterning of the dielectric layer 173 is usually performed without the presence of a mask, thus affecting the whole surface of the integrated circuit 100.
As shown in FIG. 1b, spacer-1 structures 171sp1-174sp1 have different thicknesses from each other. More specifically, spacer-1 structures 171sp1 and 172sp1 of FETs 151 and 152 are considerably thicker than spacer-1 structures 173sp1 and 174sp1 of FETs 153 and 154. This is due to the fact that the semiconductor alloy material 122-124 overfilling the trenches between and around FETs 153 and 154 causes the thickness of the portion of conformal nitride layer 173 lying above FETs 153 and 154 to decrease with respect to the thickness of the portion of conformal nitride layer 173 lying above FETs 151 and 152.
While FIGS. 1a and 1b show the process flow for an HKMG structure, the skilled person will understand that the same thickness constraints for the spacer-1 structures will result in a SiON/polysilicon gate structure process due to the raised surface portion of the eSiGe in the trench between FETs 153 and 154.
The large thickness of spacer-1 structures 171sp1 and 172sp1 results in a high aspect ratio of the gap between FETs 151 and 152. In general, the aspect ratio of an aperture is defined as the ratio of the length (dimension along the vertical axis in the figures) to the width (dimension along the horizontal axis in the figures) of the aperture.
As a result of the patterning process of conformal nitride layer 173, the distance between spacer-1 structures 171sp1 and 172sp1 shown in FIG. 1b is considerably less than the distance between spacer-1 structures 173sp1 and 174sp1. Therefore, the portion of the surface of the semiconductor layer 110 included between FETs 151 and 152 is much smaller than that included between FETs 153 and 154.
FIG. 1c shows a cross-sectional view of the integrated circuit 100 in a subsequent manufacturing stage to that shown in FIG. 1b. After forming spacer-1 structures 171sp1-174sp1 as described above, a further series of ion implantations may be performed. For example, during this series of implantations, doping agents may be implanted in active region 112 in order to form deep regions (not shown) of source and drain regions of FETs 151 and 152. Thereafter, an annealing step is performed in order to activate the implanted ions and to let the semiconductor layer 110 recover from implantation damage.
After the annealing step, a further etching is performed on the surface of the integrated circuit 100 in order to remove the exposed portion of the oxide liner layer 167, i.e., the portion of the oxide liner layer 167 not lying underneath one of the gate structures 151g-154g or of the spacer structures 171-174. FIG. 1c shows the integrated circuit 100 after this oxide liner removal process. After removing the exposed portion of the oxide liner layer 167, the gate material 165 is exposed in the gate structures 151g-154g. Furthermore, portions of the surfaces of the active regions 112 and 114 are left exposed between and around FETs 151-154. It should be noted that, after the exposed portions of the oxide liner layer 167 have been removed, the aspect ratio of the gap between FETs 151 and 152 is increased.
FIG. 1d shows that a silicidation process 181 is carried out on the integrated circuit 100 after removing the exposed liner layer 167. The silicidation process 181 is carried out in order to decrease the contact resistance to the electrodes of FETs 151-154. Silicidation 181 is performed according to a well-established procedure.
Salicidation (i.e., self-aligned silicidation) 181 is typically performed by depositing a refractory metal layer onto the exposed face of the integrated circuit 100. The refractory metal layer may comprise, for example, a metal such as nickel, titanium, cobalt and the like. Preferably, the refractory metal layer comprises nickel. The refractory metal layer may also comprise platinum, which, in some cases, may promote a more homogeneous formation of nickel monosilicide.
A heat treatment is then applied to the semiconductor structure 100 in order to promote a chemical reaction between the metal atoms of the deposited layer and the silicon atoms of the exposed surface of the semiconductor structure 100.
FIG. 1d shows that, as a result of the heat treatment, metal silicide layers 151gs-154gs have formed partly in and partly on top of the gate material 165 of the gate structures of FETs 151-154. Furthermore, metal silicide layers 140 and 141 have formed partly in and partly on top of the first active region 112, so as to provide electrical contacts with a low contact resistance to the source and drain regions of transistors 151 and 152. Analogously, metal silicide layers 142-144 have formed partly in and partly on top of the semiconductor alloy layers 122-124, respectively, so as to provide electrical contacts with a low contact resistance to the source and drain regions of transistors 153 and 154. More specifically, metal silicide layers 142-144 have formed in top portions 122c-124c of the semiconductor alloy layers 122-124, respectively. Typically, metal silicide layers 151gs-154gs and 140-144 comprise nickel silicide.
Due to the proximity of spacer-1 structure 171sp1 to spacer-1 structure 172sp1, metal silicide layer 140 formed between FETs 151 and 152 is much smaller than metal silicide layer 143 formed between FETs 153 and 154. In particular, the width (dimension along the horizontal direction in FIG. 1d) of metal silicide layer 140 is much less than the width of metal silicide layer 143. This results in a significantly higher contact resistance of metal silicide 140 as compared to metal silicide layer 143. For example, the contact resistance to the source and drain regions of FETs 151 and 152 has been measured to be up to 50% greater than the contact resistance to the source and drain regions of FETs 153 and 154.
After the silicidation process 181, an internally stressed layer (not shown) is normally deposited on the surface of the integrated circuit 100 in order to improve the device performance. The stressed layer is to fill all void spaces and gaps between neighboring FETs 151-154. However, due to the high aspect ratio of the gap between FETs 151 and 152, the stressed layer cannot easily be deposited between FETs 151 and 152.
In order to favor the deposition of the stressed layer, a further dry etching process 182 is required, which is shown in FIG. 1e. Dry etching 182 is performed on the surface of the integrated circuit 100 after performing the silicidation process 181 and is preferably selective to oxide liner layer 167. FIG. 1e shows the integrated circuit 100 after dry etching 182 has been carried out. Etching 182 causes the width of spacer-1 structures 171sp1-174sp1 to shrink. In particular, the purpose of etching 182 is decreasing the thickness of spacer-1 structures 171sp1 and 172sp1, thereby increasing the aspect ratio of the gap between FETs 151 and 152. In this manner, the stressed layer may be more effectively deposited on the surface of the integrated circuit 100.
Etching 182 is normally performed without the presence of a mask and, consequently, affects the entire exposed surface of the integrated circuit 100, not only spacer structures 171-174. In particular, etching 182 removes a surface layer of metal silicide layers 151gs-154gs and 140-144. The thickness of the removed metal silicide layer ranges between approximately 2 nm and 5 nm. This results in a further increase of the contact resistance of metal silicide layers 151gs-154gs and 140-144.
Etching 182, although rendered necessary by the traditional manufacturing flow, is desirably omitted. Besides introducing a further step in the fabrication flow, etching 182 undesirably erodes metal silicide layers 151gs-154gs and 140-144. Furthermore, etching 182 is unduly performed on the entire surface of the integrated circuit 100, whereas the effect of spacer structure thinning is only required on FETs 151 and 152, which can be, for example, N-channel FETs. The reader is here reminded that the spacer structures of FETs 153 and 154, which may be P-channel FETs, have a satisfactory thickness also before performing etching 182.
The limitations and problems outlined above become more critical the more the distance between neighboring FETs decreases in an integrated circuit. This situation calls for an improved manufacturing flow, capable of compensating for the thickness imbalance between spacer structures of, for example, N-channel FETs and P-channel FETs.